At present, capacitive networks are used for analog/digital converters (ADCs), for example for successive approximation converters, also known as Successive Approximation Register (SAR) converters. Capacitive networks include several switched capacitors, respectively having different capacitive values. Generally, an analog/digital converter of the “n-bit” type makes it possible to convert an analog signal into an n-bit digital word, and the resolution of the converter is then said to be equal to n bits.
FIG. 1 schematically illustrates a partial example of a converter CONV1 of the three bits b0, b1, b2 type, known to those skilled in the art. The switched capacitive network of this converter is coupled to a comparator COMP and includes three capacitors having capacitive values equal to Cref, 2Cref, and 4Cref respectively. Furthermore, the comparator COMP is coupled to a register REG which controls the various switches connected to the capacitors. Each capacitor makes it possible to determine a bit of the digital word corresponding to the analog signal to be converted. The capacitor having the smallest capacitance Cref is associated with the low-order bit b0 of the converter, and that having the largest capacitance 4Cref is associated with the high-order bit b2.
FIG. 2 schematically illustrates a three-quarter view of an embodiment of a conventional capacitive network RC2 of a converter of the three bits b0, b1, b2 type. The capacitive network RC2 comprises an electrically conducting comb 2 including eight identical teeth 6b to 6i forming first electrodes of seven elementary capacitors. The capacitive network RC2 furthermore includes seven electrically conducting fingers 3b to 3h so as to form the second electrodes of the seven elementary capacitors. Each second electrode is coupled to one of the connection tracks b0, b1, b2 respectively associated with the three bits b0, b1, b2 of the converter.
The first connection track b0 is associated with the low-order bit b0 of the converter, and the third track b2 is associated with the high-order bit b2. The capacitive network RC2 includes three capacitors respectively coupled to the three connection tracks b0, b1, b2. Each capacitor is represented by a finger-teeth set. The first fingers-teeth set includes a single reference finger 3e extending between two teeth 6e, 6f of the comb 2. The finger-teeth set thus forms a reference capacitor having a reference capacitive value Cref (bit b0).
The second finger-teeth set comprises two fingers 3c, 3g coupled to the second connection track b1. The capacitive value of the second set (second capacitor) is equal to twice the reference capacitance (bit b1). The third finger-teeth set (third capacitor) comprises, for its part, four fingers 3b, 3d, 3f, 3h coupled to the third connection track b2. The capacitive value of the third set is equal to four times that of the reference capacitance (bit b2). Each finger of the second and third sets are situated on either side of the reference finger 3e. Such a converter of three-bit type includes capacitors having capacitances whose values form a geometric series with ratio two, Cref, 2Cref, 4Cref.
In this embodiment of the prior art, all the elementary capacitors are identical.
U.S. patent application US 2006/0270145 also describes a capacitive network comprising a comb comprising several teeth, and several capacitors, each capacitor comprising one or more fingers linked together, with each finger being nested between two teeth of the comb and being identical to the other fingers.
At present, when it is desired to increase the resolution of a converter, it is necessary to increase the number of elementary capacitors, that is to say to increase the number of fingers and of teeth.
Given that the capacitive values form a geometric series with ratio two, as does the number of fingers, if it is desired to increase the resolution of an “n-bit” converter by one bit, it is necessary to add 2n elementary capacitors, that is to say 2n fingers. For example, to obtain a converter of four-bit type, it is necessary to add eight elementary capacitors (eight fingers) to the capacitive network RC2 of the converter of three-bit type. Increasing the number of elementary capacitors gives rise to an increase in the number of signals associated with the bits of the converter and therefore a decrease in the speed of processing of the analog input signal. It also gives rise to an increase in the size of the converters and therefore that of the integrated circuits using these converters.